Computer Organization

Circuit Design 0

D Flip-Flop using JLS

Due: Friday, September 27 at 3pm



Simulate a D flip-flop using JLS as outlined in the reading. The flip-flop should be constructed using two D latches and an inverter. The D latch should be constructed using an S-R (set-reset) latch, two AND gates and an inverter. The S-R latch should be constructed using two NOR gates. (There are four relevant diagrams in the reading: schematics for S-R and D latches and a D flip-flop and an example signal trace for the flip-flop.)

Submit one JLS file (as an attachment replying to the official email announcing this assignment). Name your file as dff_yourname.jls where yourname is either your username or the name you generally go by. (I don’t care which - as long as I can easily distinguish your circuits. For example, mine could be dff_msiff.jls or dff_mike.jls.) The attached circuit file should consist of a top-level tester circuit and three subcircuits:

The top-level “tester” circuit should include a signal generator and probes to test the D flip-flop. When the top-level circuit is run in simulation it should produce a signal trace that convincingly demonstrates that the flip-flop works as intended: on a falling C (clock) input, the value of D gets set as the memory value in the flip-flop (reflected in the Q output) and that that value remains the output regardless of the D input until the next falling C signal.

An example timing diagram:

example timing diagram
example timing diagram

Include comments in the signal-generator specification to indicate the reasoning behind the input values it produces.

Include a text element in your top-level circuit with your name.