;--------------------------------------- ; Inverter ; INPUT: a block of 0's and 1's ; EXAMPLE: 11000101 0 * * * s1 s1 0 1 R s1 s1 1 0 R s1 s1 _ _ * halt ;--------------------------------------- ; Eraser ; INPUT: a block of 0's and 1's ; EXAMPLE: 11000101 0 * * * s1 s1 0 _ R s1 s1 1 _ R s1 s1 _ _ * halt ;--------------------------------------- ; Zigzag ; INPUT: a block of 0's and 1's ; EXAMPLES: 10101, 1001000, 111 0 * * * s1 s1 0 0 R s1 s1 1 1 R s1 s1 _ _ L s2 s2 0 0 L s2 s2 1 1 L s2 s2 _ _ R s1 ;--------------------------------------- ; Looper ; INPUT: a block of 0's and 1's ; EXAMPLES: 00000, 0001111, 111 0 * * * s1 s1 0 0 R s1 s1 1 1 L s1 s1 _ _ * halt ;--------------------------------------- ; Unary Multiplication ; INPUT: two blocks of 1's separated by # ; EXAMPLE: 11#111 0 * * * s1 s1 1 $ R s2 s2 1 1 R s2 s2 # # R s3 s3 1 a R s4 s4 1 1 R s4 s4 _ _ R s5 s5 _ 1 R s6 s5 1 1 R s5 s6 1 1 R s6 s6 _ _ L s7 s7 1 1 L s7 s7 _ _ L s8 s8 1 1 L s8 s8 a a R s9 s9 a a R s9 s9 1 a R s4 s9 _ _ L s10 s10 1 1 L s10 s10 # # L s11 s10 a 1 L s10 s11 1 1 L s11 s11 a a R s12 s11 $ $ R s12 s12 a a R s12 s12 1 a R s2 s12 # # L s13 s13 a 1 L s13 s13 $ _ R s14 s14 # _ R s14 s14 1 _ R s14 s14 _ _ R halt ;--------------------------------------- ; Unary Divisor Tester ; INPUT: two blocks of 1's separated by # ; EXAMPLE: 111#111111 0 * * * s1 s1 1 1 R s1 s1 # _ R s2 s1 x x R s1 s2 _ _ L s3 s2 1 1 L s4 s2 x x R s2 s3 _ _ R s13 s3 1 1 L s3 s3 x 1 L s3 s4 _ _ L s5 s4 1 1 L s4 s4 x x L s4 s5 _ _ R s9 s5 1 x R s6 s5 x x L s5 s6 _ _ R s7 s6 1 1 R s6 s6 x x R s6 s7 _ _ L s10 s7 1 x L s8 s7 x x R s7 s8 _ _ L s5 s8 1 1 L s8 s8 x x L s8 s9 _ _ R s2 s9 1 1 R s9 s9 x 1 R s9 s10 _ _ L s11 s10 1 1 L s10 s10 x 1 L s10 s11 _ _ R s12 s11 1 1 L s11 s11 x 1 L s11 s12 _ _ R s17 s12 1 1 R s12 s12 x 1 R s12 s13 1 1 R s13 s13 _ _ R s14 s14 _ y R s15 s15 _ e R s16 s16 _ s R halt s17 1 1 R s17 s17 _ _ R s18 s18 _ n R s19 s19 _ o R halt ;--------------------------------------- ; Unary Primality Tester ; INPUT: a block of two or more 1's ; EXAMPLE: 11111 0 * * * s1 s1 _ _ R s1 s1 1 1 L s2 s2 _ _ L s3 s2 1 _ L s3 s2 x _ L s3 s3 _ 1 L s4 s3 1 1 L s4 s3 x 1 L s4 s4 _ 1 R s5 s4 1 1 R s5 s4 x 1 R s5 s5 _ _ * s6 s5 1 1 R s5 s5 x x R s5 s6 _ _ R s7 s6 1 1 R s6 s6 x x R s6 s7 _ _ L s8 s7 1 1 L s9 s7 x x R s7 s8 _ x L s20 s8 1 1 L s8 s8 x 1 L s8 s9 _ _ L s10 s9 1 1 L s9 s9 x x L s9 s10 _ _ R s14 s10 1 x R s11 s10 x x L s10 s11 _ _ R s12 s11 1 1 R s11 s11 x x R s11 s12 _ _ L s15 s12 1 x L s13 s12 x x R s12 s13 _ _ L s10 s13 1 1 L s13 s13 x x L s13 s14 _ _ R s7 s14 1 1 R s14 s14 x 1 R s14 s15 _ _ L s16 s15 1 1 L s15 s15 x 1 L s15 s16 _ _ R s17 s16 1 1 L s16 s16 x 1 L s16 s17 _ _ L s18 s17 1 1 R s17 s17 x 1 R s17 s18 _ 1 R s19 s18 1 1 L s18 s19 _ _ * s6 s19 1 1 R s19 s20 _ _ R s22 s20 1 1 L s20 s20 x x L s20 s21 _ _ L s23 s21 1 1 R s21 s21 x x R s21 s22 1 _ R s21 s22 x x R s24 s23 1 _ L s20 s24 _ _ L s26 s24 1 1 L s25 s25 x x R s27 s26 x p * halt s27 1 _ R s27 s27 _ _ L s28 s28 _ _ L s28 s28 x c * halt ;--------------------------------------- ; Binary Add1 ; INPUT: a number in binary ; EXAMPLE: 101 0 * * * s1 s1 0 0 R s1 s1 1 1 R s1 s1 _ _ L s2 s2 0 1 * s3 s2 1 0 L s2 s2 _ 1 * s3 s3 0 0 L s3 s3 1 1 L s3 s3 _ _ R halt ;--------------------------------------- ; Decimal Add1 ; INPUT: a number in base 10 ; EXAMPLE: 79 0 * * * s1 s1 * * R s1 s1 _ _ L s2 s2 0 1 * s3 s2 1 2 * s3 s2 2 3 * s3 s2 3 4 * s3 s2 4 5 * s3 s2 5 6 * s3 s2 6 7 * s3 s2 7 8 * s3 s2 8 9 * s3 s2 9 0 L s2 s2 _ 1 * s3 s3 * * L s3 s3 _ _ R halt ;--------------------------------------- ; 2-State Busy Beaver ; INPUT: blank tape 0 * * * s1 s1 _ 1 R s2 s1 1 1 L s2 s2 _ 1 L s1 s2 1 1 R halt ;--------------------------------------- ; 3-State Busy Beaver ; INPUT: blank tape 0 * * * s1 s1 _ 1 R s2 s1 1 1 L s3 s2 _ 1 L s1 s2 1 1 R s2 s3 _ 1 L s2 s3 1 1 R halt ;--------------------------------------- ; 4-State Busy Beaver ; INPUT: blank tape 0 * * * s1 s1 _ 1 R s2 s1 1 1 L s2 s2 _ 1 L s1 s2 1 _ L s3 s3 _ 1 R halt s3 1 1 L s4 s4 _ 1 R s4 s4 1 _ R s1 ;--------------------------------------- ; 5-State Busy Beaver (5a) ; INPUT: blank tape 0 * * * s1 s1 _ 1 R s2 s1 1 _ L s3 s2 _ 1 R s3 s2 1 1 R s4 s3 _ 1 L s1 s3 1 _ R s2 s4 _ _ R s5 s4 1 1 R halt s5 _ 1 L s3 s5 1 1 R s1 ;---------------------------------------